An industry wide problem exists with scaling of infrared emitter arrays up to extremely large formats. Single silicon chip arrays beyond 1024×1024 pixels fail to yield, thus creating a producibility problem and effectively limiting the size of single-chip emitter arrays. The need for larger arrays goes unmet due to this physical size restriction and is aggravated by thermal constraints of existing packaging architectures. Creating a multi-chip emitter array can avoid the single chip producibility problem. Multi-chip emitter arrays, however, introduce other problems, including the need for individual “subarrays” to be precisely aligned on the package and be maintained in a stress-free alignment through a wide temperature range. The package, therefore, has become the limiting factor in emitter array size for both single chip and multi chip configurations, particularly when operating at cryogenic temperatures.
In addition, because infrared emitter arrays are high power devices, extending the array size creates a further problem of packaging the emitter array for operation away from the assembly temperature. Coefficient of Thermal Expansion (CTE) of an array is substantially different from CTEs of most packaging materials. Therefore, emitter arrays for use at extreme temperatures, such as cryogenic environments, can suffer catastrophic stress failure when packaged using historical materials such as ceramics, copper and epoxies. Maintaining chip temperature at high power levels also is quite difficult because of the number of thermal interfaces created through the use of stress limiting features.
The historic limitations of chip yield and thermal stress serve as a roadblock to producing very large format high power emitter arrays or integrated circuits to be operated both at room and cryogenic temperatures.
The present invention overcomes the limitations on package size for emitter arrays and integrated circuits by using new materials and assembly techniques to facilitate splitting the emitter array into several precisely aligned subarrays and preserving stress-free alignment and thermal conductivity at all required temperatures. The invention also addresses thermal stress issues encountered by very large format monolithic architectures operating at cooled or cryogenic temperature. The present invention provides the thermal, electrical, and mechanical interfaces, while allowing for precise mechanical alignment and then preserving that alignment over a wide range of temperatures. The present invention also allows the size of infrared emitter arrays to be expanded to sizes demanded by current and future markets.
During cryogenic cooling, coolant can warm to its vaporization temperature, creating heat and/or pressure differential issues. Entrapping large volumes of coolant within an interior cavity, or otherwise hindering the large volume of coolant from exiting the interior cavity, can exacerbate the associated risks. U.S. Patent Application Ser. Nos. 61/844,246, filed Jul. 9, 2013, Ser. No. 14/327,307, filed Jul. 9, 2014 and issued as U.S. Pat. No. 9,706,655, and Ser. No. 15/589,431, filed May 8, 2017, the entire disclosures of which are incorporated herein by reference, disclose superior systems for and methods of cooling high-powered components, including some systems for and/or methods of reducing or eliminating risks associated with coolant vaporization.